Electrical or digital logic circuits that include flip-flop architectures are increasingly being reduced in size to accommodate the increasing number of electrical circuits formed on semiconductor chips. This is known as circuit scaling, which has reduced gate capacitance thereby increasing sensitivity to radiation induced soft errors. Circuit scaling has also reached a point of maximum clock frequency to maintain acceptable energy consumption.
Electronic circuit scaling is occurring in tandem with a desire to explore space more extensively. As the amount of electrical charge needed to flip a computer bit to a different digital logic state is reduced with scaling, radiation effects are causing problems in integrated circuits. Triple Modular Redundancy (TMR), watch dog timers, and majority voting techniques have been commonly used to reduce the impact of radiation effects on the outputs of integrated circuits. However, the area and power overhead involved in designing such protection circuits is extremely high and increases the inefficiency and complexity of integrated circuits.
Of particular importance in electronic circuit scaling are flip-flop architectures that are commonly used to store flip-type logical states, such as “High” or “Low” logic states stored in binary logic circuits. One known problem with the scaling down of flip-flop circuits is that the circuits are vulnerable to inadvertent fluctuations in their logic states due to interference from high-energy subatomic particles or electromagnetic radiation. This problem is of particular concern for certain applications of flip-flop circuits, such as flight, outer space, and nuclear applications.
New flip-flop circuits are desired that can reduce power consumption. It is additionally desirable to have flip-flop circuits that are radiation hardened against soft errors. One specific type of flip-flop circuits are dual data rate (DDR) flip-flop circuits. Conventional DDR flip-flop circuits can be classified into: (1) dual edge triggered flip-flop circuits, (2) explicit pulsed dual edge flip-flop circuits, and (3) implicit pulsed dual edge flip-flop circuits. A dual edge triggered flip-flop scheme is shown in FIG. 1(a). Although this technique helps reduce the clock frequency by half, it doubles the area required to form the flip-flop circuit on a semiconductor chip and also increases the load on the data and the clock inputs.
The explicit pulsed dual edge flip-flop scheme is as shown in FIG. 1(b). In this scheme, even though the clock frequency becomes half, an effective activity factor of the clock distribution network increases as each clock edge is replaced by two edges of the clock pulse. Moreover, the number of transistors used in the clock system increases in order to accommodate for the pulse generation. Implicit pulsed dual edge flip-flops use two series devices embedded in the logic branch receiving a clock and a delayed clock respectively. A general scheme is shown in FIG. 1(c).
FIG. 1(d) shows a conventional dual edge static hybrid flip-flop circuit (ep-DSFF). This circuit has a low power delay product compared to other conventional flip-flop circuits. The design has an explicit dual edge-triggered pulse generator and a high level triggered latch circuit. The pulse generator used in this circuit can be local to each flip-flop or shared among multiple flip-flops. Since the entire latch is not duplicated, the area overhead is relatively small. FIG. 1(e) shows the waveforms for the input, clock, and output of the ep-DSFF.
A typical electronic circuit that utilizes a flip-flop architecture is shown in FIG. 2(a). This electronic circuit is a sequential two latch structure implemented in a conventional D flip-flop circuit. A clock and data input “Data_in” provide inputs to a high level triggered latch circuit and a low level triggered latch circuit. An output L1 from the high level triggered latch circuit is inverted and then provided as a high level triggered latch circuit output to the low level triggered latch circuit. Similarly, an output from the low level triggered latch circuit L2 is inverted and provided as a “Data_out” output for the dual edge triggered flip-flop circuit. In certain instances, flip-flip circuits such as the conventional D flip-flop circuit of FIG. 2 are subjected to a radiation effect that is referred to a single event effect (SEE). This may occur when a high energy particle passes through an electronic circuit formed on a semiconductor chip. A particular node (shown as dots in FIG. 2) of an electronic circuit may receive a charge transferred from the high energy particle interacting with the semiconductor material forming the integrated circuit. The change in charge level at a particular node of the electronic circuit may result in a logic state of the node being altered. This change in logic state at a node may be particularly problematic for a flip-flop circuit since the change in the logic state at one node may affect the overall output of the flip-flop circuit. Generally, when an electronic circuit has a change in output due to an altered node voltage, then this event is referred to as a single event upset (SEU).
SEUs pose a major challenge for an error free electric circuit operation. Unlike the other components in a digital electronics system that can be protected from SEUs by logical masking, electrical masking and temporal masking, electrical circuits forming latching elements such as flip-flop circuits and latch circuits do not have immunity to SEUs. A radiation strike on a latching element is almost certain to propagate to the next stage of an integrated circuit. In addition, power consumption of such electronic circuits has become a bottleneck for technology advancement.
Other conventional flip-flop circuits include simplified B-SER-FF designs. A typical computer simulated output for this circuit is shown in FIG. 3. The waveform marked as “D_in” represents the data input to the respective flip-flop design. The waveform marked as “D_out” represents the output signal from the respective flip-flop design, and the waveform “CLK” represents the clock given to a respective flip-flop design. The waveform marked as “Simulated SEU” represents the artificial particle strikes in the form of current spikes given to the respective flip-flop design for SEU immunity testing. A computer simulated output for a B-SER-FF circuit using a conventional dual edge triggered technique is shown in FIG. 4. For either of the outputs, the B-SER-FF circuit designs have problems with SEU immunity, and may provide incorrect outputs when an SEU event occurs.
In order to avoid SEUs from occurring in integrated circuits, it is desirable to design electronic circuits that are radiation hardened. Radiation hardening reduces changes in outputs of electronic circuits due to SEUs. The conventional radiation hardening process includes adding additional electronic circuits to the integrated circuit and/or utilizing special materials in integrated circuit manufacture to reduce the effects of high energy particles interacting with the integrated circuits.
Conventional DDR flip-flop circuits are used in many desktop computers and FPGA boards. However, the existing design methodologies are too complicated and/or consume too much power due to the use of pulse generators that create pulses at each edge of the clock. These conventional DDR flip-flop circuits have a dual edge triggered ability by using a pulse generator. However, in the pulse generator circuitry, the pulsed clock has twice as much switching activity as the normal clock signal (each edge of the clock becomes a pulse with two edges). Therefore, the dynamic power consumption of the clock distribution network in conventional DDR flip-flop circuits is large. To maintain the performance of digital circuit systems, while reducing the energy consumption, implementation of new DDR flip-flop circuits is desired.
Technology advancements are demanding higher throughput and data rates at lower energy consumption rates while maintaining stable electronic circuits that are radiation hardened. In order to overcome these challenges, it is desirable that new electronic circuit designs having, for example, scaled down flip-flop and latch architectures address the problems associated with SEU occurrences in these circuits. Moreover, it is especially desirable that these problems be addressed for flip-flop architectures that improve clock frequencies, such as flip-flop circuits that increase clock frequencies by use of both edges of a pulsed clock input. The present invention satisfies these various demands.